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Impact of Circuit Placement on Single Event Transients in 65 nm Bulk CMOS Technology

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9 Author(s)
He Yibai ; Sch. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha, China ; Chen Shuming ; Chen Jianjun ; Chi Yaqing
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Heavy ion experiments on 65 nm bulk CMOS inverter chains demonstrate the impact of circuit placement on single-event transients (SETs). Experimental data and simulations show that the horizontal placement design significantly reduces the SET pulse width and SET cross-section compared to the vertical placement design due to the existence of pulse quenching.

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Nuclear Science, IEEE Transactions on  (Volume:59 ,  Issue: 6 )