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Scalable and retargetable debugger architecture for heterogeneous MPSoCs

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4 Author(s)
Luis Gabriel Murillo ; Institute for Communication Technologies and Embedded Systems (ICE), RWTH Aachen University Aachen, Germany ; Julian Harnath ; Rainer Leupers ; Gerd Ascheid

The increasing heterogeneity and parallelism of modern multi-processor systems on chip (MPSoCs) demand the evolution of existing debuggers in order to keep software development feasible. Such evolution will only be granted if upcoming software debuggers address key issues like abstraction, retargetability, scalability and convergence of information from different data sources. This paper presents a novel component-based, tree-aggregated debugger architecture which (i) grants flexibility and retargetability to deal with heterogeneous MPSoCs, and (ii) provides a framework to abstract complex details in order to facilitate debug of concurrency bugs. The debugger architecture is evaluated on an industrial-strength MPSoC virtual platform for mobile computing and next generation wireless communications.

Published in:

System, Software, SoC and Silicon Debug Conference (S4D), 2012

Date of Conference:

19-20 Sept. 2012