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This study presents the algorithm and architecture of the decimal floating-point (DFP) antilogarithmic converter, based on the digit-recurrence algorithm with selection by rounding. The proposed approach can compute faithful DFP antilogarithmic results for any one of the three DFP formats specified in the IEEE 754-2008 standard. The proposed architecture is synthesised with an STM 90-nm standard cell library and the results show that the critical path delay and the number of clock cycles of the proposed Decimal64 antilogarithmic converter are 1.26 ns (28.0 FO4) and 19, respectively, and the total hardware complexity is 29325 NAND2 gates. The delay estimation results of the proposed architecture show that it has a significant decrease in terms of latency in contrast with recently published high performance decimal CORDIC implementations.