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PWM Control Architecture With Constant Cycle Frequency Hopping and Phase Chopping for Spur-Free Operation in Buck Regulators

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2 Author(s)
Chengwu Tao ; Electrical and Computer Engineering Department, Power Management Research Laboratory, Iowa State University, Ames, IA, USA ; Ayman A. Fayed

This paper introduces a new Pulse-Width Modulation (PWM) control scheme for buck regulators that combines phase chopping with frequency hopping to achieve spur-free operation while delivering low output noise floor with no subharmonics due to hopping. The proposed regulator hops between two, four, or eight switching frequencies, but chops their phases to fully eliminate spurs, even with only two frequencies. Peaking in the noise floor around the eliminated spurs is minimized by hopping as fast as every switching cycle, and by spacing the frequencies 0.5 MHz apart. This results in less than 1.7% drop in the regulator's efficiency and less than 4 mV increase in the voltage ripple. Implemented in standard 0.35- μm CMOS technology, the proposed regulator's area and power overhead beyond conventional single-switching-frequency design is only 8% and 3%, respectively. With a spur-free spectrum and low noise floor across all frequencies, the proposed architecture can serve as a low-noise regulator for powering noise-sensitive loads without post linear regulation or additional passive filtering. Moreover, spur-free operation facilitates its integration in mixed-signal systems on chip without interfering with sensitive circuits that share the same substrate or power rails. The proposed architecture is also a good candidate for implementing class-D amplifiers, as it preserves the control loop's linearity.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:21 ,  Issue: 9 )