Referenced Items are not available for this document.
An automatic test pattern generation program (ATPG) is described for large, application-specific integrated circuits (ASICs) designed with a scan path technique. This program was implemented with an improved deterministic test generation algorithm that makes use of a split model for circuit representation and multiple testability heuristics for efficient search. The program can also interface to a hardware accelerator to speed up the test compaction process
Published in:
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Date of Conference: 2-4 Oct 1989
- Page(s):
- 244 - 248
- Meeting Date :
- 02 Oct 1989-04 Oct 1989
- Print ISBN:
- 0-8186-1971-6
- INSPEC Accession Number:
- 3730545
- Conference Location :
- Cambridge, MA
- Digital Object Identifier :
- 10.1109/ICCD.1989.63364
- Product Type:
- Conference Publications
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