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Verifying pipelined hardware using symbolic logic simulation

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2 Author(s)
Bose, S. ; Carnegie Mellon Univ., Pittsburgh, PA, USA ; Fisher, A.L.

A method is presented for automated verification of synchronous pipelined circuits, based on symbolic simulation and the well-known program verification concept of representation functions. The use of representation functions to allow straightforward formulation of readable and intuitive specifications is demonstrated, along with the use of a symbolic switch-level simulator to automatically prove that a circuit meets its specification. As an example, a systolic stack with more than 5000 transistors can be formally verified in a few minutes on a VAX 8800

Published in:

Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on

Date of Conference:

2-4 Oct 1989