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Formal verification of state-machines using higher-order logic

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1 Author(s)
Loewenstein, P.N. ; Nat. Semicond. Corp., Santa Clara, CA, USA

A description is given of the formalization of some state-machine theory in a higher-order logic (HOL) theorem prover and the results obtained applying that theory. It is shown that by building state-machine theory in HOL, the verification of state-machines is rendered much more tractable. This is illustrated using a family of redundantly encoded serial-parallel multipliers

Published in:

Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on

Date of Conference:

2-4 Oct 1989