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An efficient architecture for stereo vision implementation on FPGAS using low and high level image features

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4 Author(s)
Elhossini, A. ; Fac. of Eng., Azhar Univ., Cairo, Egypt ; Moussa, M. ; Tarry, C. ; de Brito, C.

In this paper we present a new architecture for implementing real-time stereo vision on FPGA chips. The proposed architecture is based on reducing the computational needs by focusing on specific image features only instead of processing every image pixel. Two classes of features are considered. The first are low level features like edges and the second are high level features like complete patterns or regions. The paper discusses how both types of features can be integrated with depth calculations to reduce the required FPGA resources while maintaining real-time performance. This allows implementation on relatively small FPGA chips or when limited resources are available. The proposed architecture was successfully implemented on a Virtex 4 FPGA and tested using several sample data sets. The results show that the proposed architecture has excellent accuracy coupled with a significant reduction in required resources.

Published in:

Electrical & Computer Engineering (CCECE), 2012 25th IEEE Canadian Conference on

Date of Conference:

April 29 2012-May 2 2012