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Using indirection to minimize message delivery latency on cache-less many-core architectures

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3 Author(s)
Kroeker, A. ; Dept. of Electr. & Comput. Eng., Univ. of Victoria, Victoria, BC, Canada ; Dimopoulos, N.J. ; Khunjush, F.

The focus of this work is on techniques that promise to reduce the message delivery latency in message passing interface (MPI) environments for cache-less systems (e.g. the Cell BE processor). Significant contributors to message-delivery latency are the message copying operations during receive. To avoid this copying overhead, we introduce architectural extensions comprising an Indirection Cache and instructions to manage the operations of this extension. This method allows the late binding of the received message by redirecting its effective address. An Indirection Buffer stores the last Receive Variable effective address and uses it predictively for subsequent accesses.

Published in:

Electrical & Computer Engineering (CCECE), 2012 25th IEEE Canadian Conference on

Date of Conference:

April 29 2012-May 2 2012