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Indirectly-compared cache tag memory using a shared tag in a TLB

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4 Author(s)
Yonghwan Lee ; Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea ; Taeyoung Lee ; Sangjun An ; Yongsurk Lee

A shared tag by which both translation lookaside buffers (TLBs) and caches can be accessed is presented. This architecture reduces the chip area of conventional cache tags and also improves the speed of cache systems. To validate the proposed architecture, the authors measured both the area and speed based on VLSI circuits

Published in:

Electronics Letters  (Volume:33 ,  Issue: 21 )

Date of Publication:

9 Oct 1997

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