Referenced Items are not available for this document.
A design-for-test (DFT) technique for analogue circuits is proposed which splits all high current transistors into two. This technique reduces the fault-masking effects of the fault-free parts of the circuit, giving a potential fault cover of over 99%. Other advantages are the small area overhead and a low performance penalty
Published in:
Electronics Letters
(Volume:33
,
Issue:
21
)
Date of Publication: 9 Oct 1997
- Page(s):
- 1746 - 1748
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 5733375
- Digital Object Identifier :
- 10.1049/el:19971174
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- 9 Oct 1997
- Sponsored by :
- Institution of Engineering and Technology
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
