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On-chip interconnection networks are fast becoming significant power consumers in high-performance chip multiprocessors. Increased power consumption leads to more heat, degrades system reliability, and may increase the cost of cooling integrated circuit packages. This situation is becoming worse as bulk CMOS technology scales further into the nanometer regime because of the excessive leakage power caused by short-channel effects. In this paper, we explore the use of FinFETs, which are promising substitutes for bulk CMOS at the 22-nm node and beyond, to design on-chip network routers. We present a detailed design of a variable-pipeline-stage router (VPSR) targeted at FinFET technology. We employ a dynamic power management scheme, which we call adaptive back-gate biasing, for FinFET implementations. We propose enhanced token flow control (ETFC), a flow control mechanism that improves upon the energy/delay/throughput of the previous state-of-the-art token flow control mechanism. We evaluate VPSR and ETFC on a simulation platform specifically designed for power/performance simulations of FinFET-based interconnection networks. The results show that VPSR is able to successfully adapt its power consumption to incoming traffic, with a resultant 21.5% reduction in power with almost no impact on latency.