By Topic

An Efficient Reconfigurable Architecture Design and Implementation of Image Contrast Enhancement Algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Wen-Chieh Chen ; Dept. of Electron. Eng., Nat. Taipei Univ. of Technol., Taipei, Taiwan ; Shih-Chia Huang ; Trong-Yen Lee

Contrast enhancement is crucial to generating high quality images in the applications of image processing such as digital image or video photography, LCD processing, and medical image analysis. In order to achieve real-time performance for high-definition video applications, it is necessary to design efficient contrast enhancement hardware architecture to meet the needs of real-time processing. In this paper, we propose a parameter-controlled reconfigurable architecture to decrease hardware cost and improve hardware utilization for the proposed contrast enhancement algorithm. The experiment results show that the proposed method can provide the average frame rate 48.23 fps at high definition resolution 1920 × 1080 which means the proposed hardware architecture can run in real-time.

Published in:

High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems (HPCC-ICESS), 2012 IEEE 14th International Conference on

Date of Conference:

25-27 June 2012