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A Study of NoC Topologies and Switching Arbitration Mechanisms

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2 Author(s)
Yung-Chang Chang ; Inf. & Commun. Res. Lab., Ind. Technol. Res. Inst., Hsinchu, Taiwan ; Ching-Te Chiu

Network-on-chip (NoC) has evolved as the promising solution for ever increasing chip level integrations. The architecture of an NoC can be specified by its topology and switching scheme. In this paper, we evaluate these design parameters with exemplified NoC realizations. We adopt popular 2D-mesh and H-star as our topology candidates. The former accompanies with a high-performance iSLIP switch architecture, while the latter utilizes the state of the art Birkhoff-von Neumann (BvN) switch architecture which can allocate the bandwidth resource depending on a specific traffic pattern. A real-world video object plane (VOP) decoder is mapped onto these platforms for the static performance benchmarking. In addition, we also implemented cycle-accurate SystemC models to probe further into the dynamic behavior on the target NoC platforms. The experimental results reveal that simple 2D-mesh outperforms the complex H-star with novel traffic awareness bandwidth allocation algorithm.

Published in:

High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems (HPCC-ICESS), 2012 IEEE 14th International Conference on

Date of Conference:

25-27 June 2012