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A Metric for Identifying Detectable Path Delay Faults

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1 Author(s)
Pomeranz, I. ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

Path delay faults are used for modeling small delay defects. Due to the large numbers of paths and the large numbers of undetectable path delay faults, test generation procedures for path delay faults use path selection procedures and procedures for the identification of undetectable faults to facilitate test generation. To complement these procedures, this paper describes a metric for assessing the likelihood that a path delay fault is detectable. Path selection procedures should prefer such faults in order to yield sets of target faults that are detectable even if not all the undetectable faults are identified prior to test generation. The metric is defined such that it allows all the path delay faults with the same value of the metric (the same likelihood of being detectable) to be enumerated together. The metric is computed based on the numbers of detections of transition faults under a test set for such faults, and requires N-detection fault simulation of transition faults for a sufficiently large value of N. The results of test generation for path delay faults confirm that faults with higher values of the metric are more likely to be detectable.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:31 ,  Issue: 11 )

Date of Publication:

Nov. 2012

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