By Topic

Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Bing Li ; Institute for Electronic Design Automation, Technische Universität München, Munich, Germany ; Ning Chen ; Ulf Schlichtmann

Level-sensitive latches are widely used in high-performance designs. For such circuits, efficient statistical timing analysis algorithms are needed to take increasing process variations into account. The existing methods for solving this problem are still computationally expensive and can only provide the yield at a given clock period. In this paper, we propose a method combining reduced iterations and graph transformations. The reduced iterations extract setup time constraints and identify a subgraph for the following graph transformations handling the constraints from nonpositive loops. The combined algorithms are very efficient, more than ten times faster than other existing methods, and result in a parametric minimum clock period, which, together with the hold-time constraints, can be used to compute the yield at any given clock period very easily.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:31 ,  Issue: 11 )