By Topic

Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Chuan Xu ; Technology Development and Innovation Group, Maxim Integrated Products, Beaverton, OR, USA ; Navin Srivastava ; Roberto Suaya ; Kaustav Banerjee

We present a high-frequency impedance extraction method for horizontal interconnects as needed in 3-D integrated circuits (ICs), where the horizontal interconnects are sandwiched between substrate layers of possibly different electromagnetic parameters. In particular, for the first time, we develop an extension of the discrete complex images method based on a 2D, or alternatively, 3D magneto-quasi-static (MQS) vector potential Green's functions to extract analytical solutions to the series impedance (resistance and inductance) matrix elements for wire filaments. We then follow standard methods to extract the port impedance. Using the 2D approach, the series impedance per unit length of horizontal wire loops is obtained, which shows excellent accuracy (<; 1% error to Maxwell SV) and significantly improved computational cost (two orders faster than Maxwell SV). Using our 3D approach and combining the series impedance matrix from the MQS extraction engine with the capacitance matrix from an electrostatic extraction engine, we produce an electro-magneto-quasi-static impedance matrix extraction engine, which is used to extract the input impedance of a spiral inductor. In the frequency range spanning near dc to a high frequency cutoff given by four times the frequency of the maximum in the quality factor, we show that our results agree to within less than 5% and 11% deviation to the full-wave simulator HFSS, for the self and mutual loop impedance, respectively. The CPU time using our approach is 18-25&times; faster than HFSS. These results provide a reasonable foundation for circuit block-level impedance extraction for interconnects and inductors in 3-D integrated systems.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:31 ,  Issue: 11 )