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By tuning the SET/RESET pulse amplitude conditions, the pulse endurance of our 40-nm HfO2/Hf 1T1R resistive-random-access-memory devices demonstrates varying failure behaviors after 106 cycles. For unbalanced SET/RESET pulse amplitude conditions, both low-resistance state (LRS) and high-resistance state (HRS) failures may occur, while varying the pulsewidths influences the LRS/HRS window and the stability of the LRS/HRS states. The failure of the HRS or LRS state during cycling is ascribed to the depletion or excess of oxygen vacancies at the switching interface. Through a dc SET/RESET recovery operation, LRS/HRS states can be recovered after failure, indicating that the distribution of oxygen vacancies can be restored. By optimally balancing the SET/RESET pulse conditions, more than 1010 pulse endurance cycles is achieved.