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A current reference pre-charged zero-crossing pipeline-SAR ADC in 65nm CMOS

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2 Author(s)
Kuppambatti, J. ; Columbia Univ., New York, NY, USA ; Kinget, P.R.

Using a current reference pre-charge technique, the need for power hungry low impedance voltage reference buffers is eliminated in a zero-crossing pipeline-SAR ADC. The 40MS/s ADC prototype, implemented in a 65nm CMOS process, achieves an SFDR/SDR/SNDR of 70dB/66dB/59.5dB at Nyquist, while occupying 0.95mm2 and consuming 4.5mW from a 1.35V supply, requiring no additional power for reference buffers.

Published in:

Custom Integrated Circuits Conference (CICC), 2012 IEEE

Date of Conference:

9-12 Sept. 2012

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