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Power efficiency has become a major issue in computer Power Management Unit (PMU) as modern Integral Circuit (IC) is scaling toward smaller feature size. In high-performance computing applications, PMU electronics suffer from extensive Process-Voltage-Temperature (PVT) variation since high-level integration has exceeded physical limit of semiconductor material. This paper provides an overview of adaptive powerperformance management with emphasis on design optimization to bound dynamic losses. The challenge on mitigating the PVT influence in a current-mode control PMU has been discussed, with emphasis on key parameters of threshold voltage and on-state resistance. A PVT compensation solution is henceforth introduced which implements on-chip sensing technology to represent the driver performance. High accurate current sensing is achieved. Featuring a synchronous DC-DC step-down voltage regulator as example, simulation results show 43% reduction on power consumption is achieved by static compensation. In addition, an Adaptive Voltage Scaling (AVS) strategy is described which is configured to alter the gate driver to optimize the power efficiency over whole operation range.
Date of Conference: 7-8 Sept. 2012