Simulation of open and shorted RC interconnect waveforms for voltage step function with low and high transient response

This paper presents the interconnect analysis of the BICMOS and ECL gates, modeled by uniformly distributed Resistance-Capacitance along the wire network for node step voltage. Open and shorted ended responses are analysed. The current and voltage are plotted for lows and high transient time /spl tau/=0.0 up to 5. Two Laplace transformations, contour integration, Heaviside theorem, and bisection technique algorithms, are used. The results show that for /spl tau/ less than 0.1 the responses oscillate around the interconnect length axis having positive and negative values while for /spl tau/ higher than 0.1 the response is totally positive which is very important criterion during design techniques.