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Simulation of open and shorted RC interconnect waveforms for voltage step function with low and high transient response

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1 Author(s)
K. M. El-Shennawy ; Acad. for Sci. & Technol. & Maritime Transp., Alexandria, Egypt

This paper presents the interconnect analysis of the BICMOS and ECL gates, modeled by uniformly distributed Resistance-Capacitance along the wire network for node step voltage. Open and shorted ended responses are analysed. The current and voltage are plotted for lows and high transient time τ=0.0 up to 5. Two Laplace transformations, contour integration, Heaviside theorem, and bisection technique algorithms, are used. The results show that for τ less than 0.1 the responses oscillate around the interconnect length axis having positive and negative values while for τ higher than 0.1 the response is totally positive which is very important criterion during design techniques

Published in:

Microelectronics, 1997. Proceedings., 1997 21st International Conference on  (Volume:2 )

Date of Conference:

14-17 Sep 1997