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Reconfigurable Processor for Binary Image Processing

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3 Author(s)
Bin Zhang ; Xi'an Jiaotong Univ., Xi'an, China ; Kuizhi Mei ; Nanning Zheng

Binary image processing is a powerful tool in many image and video applications. A reconfigurable processor is presented for binary image processing in this paper. The processor's architecture is a combination of a reconfigurable binary processing module, input and output image control units, and peripheral circuits. The reconfigurable binary processing module, which consists of mixed-grained reconfigurable binary compute units and output control logic, performs binary image processing operations, especially mathematical morphology operations, and implements related algorithms more than 200 f/s for a 1024  × 1024 image. The periphery circuits control the whole image processing and dynamic reconfiguration process. The processor is implemented on an EP2S180 field-programmable gate array. Synthesis results show that the presented processor can deliver 60.72 GOPS and 23.72 GOPS/mm2 at a 220-MHz system clock in the SMIC 0.18-μm CMOS process. The simulation and experimental results demonstrate that the processor is suitable for real-time binary image processing applications.

Published in:

Circuits and Systems for Video Technology, IEEE Transactions on  (Volume:23 ,  Issue: 5 )

Date of Publication:

May 2013

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