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Binary Multiplication Using Hybrid MOS and Multi-Gate Single-Electron Transistors

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2 Author(s)
Guoqing Deng ; Dept. of Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON, Canada ; Chunhong Chen

In this paper, we investigate the design of binary tree multipliers based on multi-input counters using hybrid MOS and single-electron transistors (SETs). Our focus is on the design of phase-modulated counters which can be implemented with only a few MOSFETs and multi-gate SETs. In order to address some practical issues associated with SET/MOS hybrid circuits, we present an enhanced version of the counters to deal with temperature effect, reliability improvement, and operating speed with multipliers. Simulation results with the proposed phase-modulated (7:3) counter show that it is able to work at room temperature with a delay of 1.5 ns, power dissipation of 4.1 μW at frequency of 100 MHz, and maximum tolerable background charges of up to 0.2e with the worst-case delay of 3 ns.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:21 ,  Issue: 9 )