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This paper introduces a novel signaling scheme for parallel high-speed interfaces. The new signaling, called coded differential (CD), maps two bits of information to four wires and, therefore, has the same pin-efficiency as differential signaling. The coding scheme is designed in such a way that the parallel interface preserves many of the attractive properties of a differential link such as low supply noise generation and immunity to common-mode noise. The CD receiver also incorporates differential detection with no need for a dc reference. In addition, the coding completely eliminates the first post-cursor intersymbol interference of the channel over the entire unit-interval at no loss in throughput. As a result, CD leads to substantial increase in timing margin compared with a differential link with 1-tap decision feedback equalizer (DFE). Unlike DFE, CD does not require channel tap estimation. The theory of CD signaling, the optimization of the encoder and the decoder, and the implementation details of a prototype system developed based on this scheme for graphics memory interfaces are described. The full-featured interface, implemented in a 40-nm CMOS process, transfers 8 × 16 Gb/s data over 16 wires and achieves an energy efficiency of 4.1 pJ/b. Eye diagram measurements on a scope indicate 30% improvement in timing margin compared with a 1-tap predictive DFE system.