By Topic

A high-speed ATM switch architecture using random access input buffers and multi-cell-time arbitration

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Hakyong Kim ; Dept. of Inf. & Commun., Kwang-Ju Inst. of Sci. & Technol., South Korea ; Changhwan Oh ; Kiseon Kim

We introduce a new high-speed ATM switch using random access input buffers (RAIB) and multi-cell-time arbitration (MCTA), and evaluate its performance for uniform traffic by a numerical method and by computer simulations. The switch has N same input modules each of which is similar to the common shared buffer switch. N address buffers (ABs) in the input module are used for the N output, and the ABs for a certain output in different input modules are controlled by an external arbitrator. The MCTA arbitration is employed in order to reduce the required arbitration rate as well as to provide the guard time when the switch is operated at a very high-speed. In MCTA arbitration, the service order of two or more cells destined for the same output is determined by one arbitration, but the cells are transmitted one by one in each time slot

Published in:

Global Telecommunications Conference, 1997. GLOBECOM '97., IEEE  (Volume:1 )

Date of Conference:

3-8 Nov 1997