A high-speed ATM switch architecture using random access input buffers and multi-cell-time arbitration

We introduce a new high-speed ATM switch using random access input buffers (RAIB) and multi-cell-time arbitration (MCTA), and evaluate its performance for uniform traffic by a numerical method and by computer simulations. The switch has N same input modules each of which is similar to the common shared buffer switch. N address buffers (ABs) in the input module are used for the N output, and the ABs for a certain output in different input modules are controlled by an external arbitrator. The MCTA arbitration is employed in order to reduce the required arbitration rate as well as to provide the guard time when the switch is operated at a very high-speed. In MCTA arbitration, the service order of two or more cells destined for the same output is determined by one arbitration, but the cells are transmitted one by one in each time slot.