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Chip-multiprocessors need low cost and high performance communication structure. Network-on-Chip (NOC) is a promising candidate because of its high scalability. In this paper, a hybrid circuit-switched (HCS) NOC is proposed. The HCS NOC uses bufferless switch and pipeline channel to construct the on-chip network. A network interface is also designed to make the HCS NOC AMBA-compatible. Packet setup channel and preserves this channel in one clock. Hence, the network transfer message with a hybrid scheme. It works as packet routing if the message has one packet or circuit switching if the message has multiple packets. Since the coherence protocol has not been ready yet, we evaluate the HCS network by random traffic pattern without processors. Our results show that the HCS network with 2-entry channel has low cost and good performance. It has 8 percent smaller cycle time, 27 percent smaller power consumption, 29 percent smaller area and 12 percent smaller maximum throughput compared to the HCS network with 4-entry channel.
Note: As originally published there was an error in this document. Due to a production error the final formatted version of paper was not submitted. A corrected replacement PDF is now provided.
Date of Conference: 24-26 Aug. 2012