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Performance analysis of wireless 3D network on chip

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5 Author(s)
Quanyou Feng ; School of Computer Science, National University of Defense Technology, Changsha, Hunan, China ; Dongson Ban ; Huanzhong Li ; Gang Han
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Interconnect infrastructure plays a crucial role in the performance of multi-core systems-on-chip (SoCs). In order to satisfy the continuing demand for energy-efficient and high-performance interconnect fabrics, three-dimensional (3-D) integration, wireless interconnects and other network-on-chip options have been envisioned respectively as compelling alternatives to the existing planar metal/dielectric communication structures. In this paper we propose a wireless 3D network-on-chip paradigm which combines potential benefits of both 3D integration and wireless Nocs. System-level performance analysis and simulations show that the hybrid architecture provides another competitive option for SoCs communication fabrics design.

Published in:

Instrumentation & Measurement, Sensor Network and Automation (IMSNA), 2012 International Symposium on  (Volume:1 )

Date of Conference:

25-28 Aug. 2012