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This paper discusses the design of low-voltage, high gain, fully differential CMOS Op-amp in a low voltage (VDD = 1.0V) 90nm CMOS process. This Op-amp is ideally suited for switch-capacitor circuits and simulations show a unity gain bandwidth of 651MHz with 1pF load capacitor and a DC gain of more than 107dB. The phase margin is around 58°. The circuit topology is a two-stage folded cascode structure with regulated cascodes for gain boosting.
Instrumentation & Measurement, Sensor Network and Automation (IMSNA), 2012 International Symposium on (Volume:1 )
Date of Conference: 25-28 Aug. 2012