By Topic

High-level model of sensor architecture for hardware and software design space exploration

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Nicolas Serna ; LEAT UNS/CNRS UMR 7268, University of Nice, France ; Fran├žois Verdier

For helping SoC designers to make right choices at the first development steps, we present here a new Hw/Sw high-level SoC model in order to facilitate the exploration. Because they offer a large optimization capacity, we particularly aim on operating system (OS) services, tasks mapping and some architectural parameters like frequency, supply voltage or data width. Simulation results provide consumption and time metrics and allow to verify our application functional validity. We focalize our work on a realistic mono-processor sensor architecture while aiming a future evolution to multi-processor and dynamically reconfigurable architecture. Our model is based on SystemC and allows very fast co-simulation including C++ tasks, OS and high-level models of the hardware architecture.

Published in:

Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2012 7th International Workshop on

Date of Conference:

9-11 July 2012