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MARTE has matured into a substantial industrially relevant profile that extends UML expressive power to support the specification and design of embedded systems. When supported by appropriate model transformation and code generation tools, MARTE forms an appropriate starting point for embedded system development. In this paper we propose a simpler yet less powerful subset of MARTE, targeted at multiprocessor systems and amenable to early analysis (including timing) of design alternatives before committing to a particular design for implementation. We use the proposed subset of MARTE constructs to generate abstract simulation and real-time schedulability analysis models, allowing both average and worst-case performance metrics to be considered when comparing multiple design alternatives.