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Power management techniques in an FPGA-based WSN node for high performance applications

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6 Author(s)
M. Lombardo ; Centre of Industrial Electronics, Technical University of Madrid, José Gutiérrez Abascal, 2; 28006 Madrid, Spain ; J. Camarero ; J. Valverde ; J. Portilla
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In this work, the power management techniques implemented in a high-performance node for Wireless Sensor Networks (WSN) based on a RAM-based FPGA are presented. This new node custom architecture is intended for high-end WSN applications that include complex sensor management like video cameras, high compute demanding tasks such as image encoding or robust encryption, and/or higher data bandwidth needs. In the case of these complex processing tasks, yet maintaining low power design requirements, it can be shown that the combination of different techniques such as extensive HW algorithm mapping, smart management of power islands to selectively switch on and off components, smart and low-energy partial reconfiguration, an adequate set of save energy modes and wake up options, all combined, may yield energy results that may compete and improve energy usage of typical low power microcontrollers used in many WSN node architectures. Actually, results show that higher complexity tasks are in favor of HW based platforms, while the flexibility achieved by dynamic and partial reconfiguration techniques could be comparable to SW based solutions.

Published in:

Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2012 7th International Workshop on

Date of Conference:

9-11 July 2012