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Low-power multiple-valued SRAM logic cells using single-electron devices

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2 Author(s)
Naila Syed ; Department of Electrical and Computer Engineering, University of Windsor, Ontario, Canada N9B 3P4 ; Chunhong Chen

This paper presents single electron tunneling (SET) based static memory cells for multiple-valued logic applications. All simulations are conducted using Monte Carlo simulation tools. In particular, a ternary SRAM cell is designed using the proposed architecture with standby power consumption of 0.98nW and logic margin of 270mV at temperature of 77K.

Published in:

Nanotechnology (IEEE-NANO), 2012 12th IEEE Conference on

Date of Conference:

20-23 Aug. 2012