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In this paper, an all-digital clock and data recovery (ADCDR) circuit is presented. The proposed ADCDR can recover the data stream sent by a transmitter with a spread spectrum clock generator (SSCG). The proposed adaptive gain control scheme can automatically adjust the phase tracking gain by counting the consecutive identical digits (CID), and the time-to-digital converter (TDC)-based fast phase compensation can quickly compensate for a large phase error. The proposed ADCDR can tolerate input peak-to-peak jitter up to 130ps at 480MHz with the down-spread 10% modulation. In addition, the bit error rate (BER) is less than 10-12 with 231-1 pseudo-random binary sequence (PRBS). The proposed ADCDR is implemented in a standard performance 65nm CMOS process with standard cells. The active area is 130μm × 100μm, and the power consumption is 1.13mW at 480MHz with the down-spread 10% modulation.
Date of Conference: 10-11 July 2012