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As Bias Temperature Instability (BTI) effects increase the threshold voltage of transistors and decrease transistors speed, it has become a major problem for circuit reliability. Retention registers are the widely used storage cells in the power gating architecture. These registers can keep the current states in the always-on blocks. However, they suffer from significant BTl effects because the always-on block suffers from significant aging effects. This paper investigates the aging effect on various D-type retention registers. First, the paper analyzes the setup, hold and required times of retention registers under differing BTl effects. Second, because the always-on block always suffers from the BTl effects, the required time to store the data in an always-on block increases by between 0.6x-1.4x in 32nm technology. Finally, the selective transistor sizing technique is used to improve the setup, hold and required times of various D-type retention registers. Increasing the sizing of transistors between 20%-90% results in an improvement between 8.9%-41.2% in both setup and hold time.