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A bias-driven approach to improve the efficiency of automatic design optimization for CMOS OP-Amps

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5 Author(s)
Ya-Fang Cheng ; Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan ; Li-Yu Chan ; Yen-Lung Chen ; Yu-Ching Liao
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The equation-based analog design automation is getting popular in last decade to search the optimal solutions with good efficiency. However, due to the deep-submicron effects, significant modeling errors often exist in major transistor parameters like gds and gm. This often results in wrong prediction of circuit performance and leads to several redesign cycles to meet the specifications. Instead of building complex parameter models for gds and gm, this paper adopts the gm/Id design concept, which is an independent value to the device size, on equation-based optimization to solve the accuracy issue. Without the complex effects from W and L, the modeling accuracy of transistor parameters is significantly improved. No more iteration is required by using the proposed approach, which improves the efficiency as well as the accuracy. To the best of our knowledge, this is the first work that adopts the internal voltages instead of device sizes as the unknown variables to be solved. As demonstrated on several circuits with different objectives, both the accuracy and efficiency of circuit optimization can be improved significantly.

Published in:

Quality Electronic Design (ASQED), 2012 4th Asia Symposium on

Date of Conference:

10-11 July 2012