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In This paper, we presents a full on-chip and area efficient low-dropout voltage regulator (LDO) which, exploiting the technique nested miller compensation with active capacitor (NMCAC) to eliminate the external capacitor without compromising the stability of the system in the full output current range. The external capacitor is removed allowing for greater power system integration for system on-chip applications. The proposed LDO is that provides a fast transient response, a low quiescent current 51 μA with a dropout voltage of 192 mV and output variation 69 mV when a full load step 0-50 mA is applied. It designed in 0.18 μm CMOS process.