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Parallel object recognition on an FPGA-based configurable computing platform

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3 Author(s)
Yongwha Chung ; Syst. Eng. Sect., Electron. & Telecommun. Res. Inst., Daejeon, South Korea ; Choi, S. ; Prasanna, V.K.

Object recognition involves identifying known objects in a given scene. It plays a key role in image understanding. Geometric hashing has been proposed as a technique for model-based object recognition in occluded scenes. However, parallel techniques are needed to realize real-time vision systems employing geometric hashing. In this paper, we develop a design technique for parallelizing geometric hashing on an FPGA-based platform. We first transform the hash table which contains symbolic data into a bit-level representation. By regularizing the data flow and exploiting bit-level parallelism in hardware, our design achieves high performance. Using our approach, given a scene consisting of 256 feature points, a probe can be performed in 1.65 milliseconds on an FPGA-based platform having 32 Xilinx 4062s. In earlier implementations, the same probe operation was performed in 240 milliseconds on a 32K-node CM2 and in 382 milliseconds on a 32-node CM5. Also, the same operation takes 40 milliseconds on a 32-node IBM SP-2. By parameterizing the application and the device characteristics, we derive an area-time efficient design based on these parameters. Furthermore, our approach can be applied to many geometric hashing methods and is portable to other FPGA devices

Published in:

Computer Architecture for Machine Perception, 1997. CAMP 97. Proceedings. 1997 Fourth IEEE International Workshop on

Date of Conference:

20-22 Oct 1997