Skip to Main Content
Reverse-bias stress testing has been applied to a large set of more than 50 AlGaN/GaN high electron mobility transistors, which were fabricated using the same process but with different values of the AlN mole fraction and the AlGaN barrier-layer thickness, as well as different substrates (SiC and sapphire). Two sets of devices having different defect types and densities, related to the different growth conditions and the choice of nucleation layer, were also compared. When subjected to gate-drain (or gate-to-drain and source short-circuited) reverse-bias testing, all devices presented the same time-dependent failure mode, consisting of a significant increase in the gate leakage current. This failure mechanism occurred abruptly during step-stress experiments when a certain negative gate voltage, or “critical voltage,” was exceeded or, during constant voltage tests, at a certain time, defined as “time to breakdown.” Electroluminescence (EL) microscopy was systematically used to identify localized damaged areas that induced an increase of gate reverse current. This current increase was correlated with the increase of EL intensity, and significant EL emission during tests occurred only when the critical voltage was exceeded. Focused-ion-beam milling produced cross-sectional samples suitable for electron microscopy observation at the sites of failure points previously identified by EL microscopy. In high-defectivity devices, V-defects were identified that were associated with initially high gate leakage current and corresponding to EL spots already present in untreated devices. Conversely, identification of defects induced by reverse-bias testing proved to be extremely difficult, and only nanometer-size cracks or defect chains, extending vertically from the gate edges through the AlGaN/GaN heterojunction, were found. No signs of metal/semiconductor interdiffusion or extended defective areas were visible. The weak dependence on AlGaN prope- ties, the strong process dependence, the time dependence, and the features of the localized damage identified by EL and electron microscopy suggest a multistep failure mechanism initiated by a process-induced weakness of the gate Schottky junction, which enhances current injection into pre-existing defects. As a result, further defects are generated or activated, eventually resulting in a percolation conductive path and permanent damage. A low-impedance path between the device gate and the channel is formed, increasing gate leakage current and possibly resulting in device burnout.