Hardware Architecture of IOTA Pulse Shaping Filters for Multicarrier Systems

This paper presents a hardware architecture of pulse shaping filter used in multicarrier systems. The filter can be configured to be used for both transmitter and receiver with limited overhead. Generic implementation complexity analysis for a filter in a multicarrier system with
N
sub-carriers is presented, while the implemented architecture is for a system with 128 sub-carriers. The pulse shaping filter is part of a larger system based on faster-than-Nyquist signaling and aided in an overall complexity reduction. Hence, designing an efficient hardware architecture to keep the overhead moderate was the motivation behind this work. Architectural optimizations has been carried out in order to reduce area and power. The implementation of the proposed hardware architecture was carried out using a 65-nm CMOS process. The chip core occupies an area of 0.11 mm
²
and is estimated to consume 14.4 mW of power when running at 200 MHz.