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Synchronization algorithm and FPGA implementation for Transmit-Reference UWB receiver

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2 Author(s)
Nguyen, H.V. ; EDA Group - C9 401, Hanoi Univ. of Sci. & Technol., Hanoi, Vietnam ; Tran, M.H.

This paper proposes a practical synchronization algorithm for Transmit-Reference UWB receiver which uses sliding window and supports flexible sampling rates. Additionally, a Simulink model and implementation of synchronization algorithm in receiver by hardware description language (HDL) is also developed using model-based design. Finally, we assess impact of signal-noise-rate (SNR), number of bits quantization and sampling rate on bit-error-rate (BER).

Published in:

Communications and Electronics (ICCE), 2012 Fourth International Conference on

Date of Conference:

1-3 Aug. 2012