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Multi-walled carbon nanotubes (MWCNTs) have attracted much attention as very large scale integration (VLSI) chip interconnects, because of their high-current densities and excellent thermal and mechanical properties. This study investigates different aspects of the use of MWCNTs as chip routing wires to seek modern technologies for high-performance interconnects. Mathematical analyses, and simulations were made for MWCNT and Cu at global, intermediate and local interconnect levels. The authors propose a semi-analytical delay estimation model along with an equivalent RC model for MWCNT global interconnects. The results obtained from these models show good conformance with the simulation results. The proposed compact semi-analytical model can be used to perform fast analysis of MWCNT global interconnects, including delay, buffer insertion and crosstalk. The authors exploited their model to investigate the impact of buffer insertion on MWCNT interconnect delay. The optimal number of required buffers is estimated, as it minimises the MWCNT propagation delay. Analytical and simulation results show that the MWCNT interconnects require lower number of buffers compared to Cu wires.