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A promising solution to continue the complementary metal-oxide semiconductor (CMOS) scaling roadmap at the 22 nm technology node and beyond is CMOS-silicon on insulator (SOI), which is used especially in low-power and "system on chip" applications. CMOS-SOI involves building conventional MOSFETs on very thin layers of crystalline silicon. The thin layer of silicon is separated from the substrate by a thick layer of buried SiO2 film, thus isolating the devices from the underlying silicon substrate and from each other. CMOS-SOI technology is already a leading technology in a wide range of applications where integrated CMOS-SOI-microelectromechanical systems or nanoelectromechanical systems (MEMS/NEMS) technologies provide unique sensing systems for IR and terahertz (THz) imagers. CMOS-SOI technology is traditionally classified into partially depleted (when the silicon device layer is thicker than the maximum gate depletion width) and fully depleted devices (when the device layer is fully depleted before the threshold voltage is reached). It may also be classified, like all CMOS technology, according to the minimal channel length, Lmin. This study focuses on partially depleted 0.18 RF CMOS-SOI technologies  with emphasis on the weak and strong inversion regions. This process is suitable for mixed-signal design because of its maturity and relatively low cost, while the methodology and results presented here may be extended to any advanced CMOS-SOI nano-transistors. The results of this study may provide a systematic approach to assessing the thermal behavior of CMOS-SOI transistors operating in a wide range of temperatures.