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A low-power 18-GHz dual-injection-locked frequency divider in 65-nm CMOS

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4 Author(s)
Dong Huang ; Dept. of Electron. Sci. & Technol., Univ. of Sci. & Technol. of China, Hefei, China ; Shengxi Diao ; Peng Wei ; Fujiang Lin

In this paper, an 18-GHz dual-injection locked frequency divider (ILFD) is presented. In order to decrease the complexity of PLL design, the dual-ILFD doesn't adopt a frequency adjustment scheme but achieves a large locking range due to fully utilizing the voltage and current injection of the input signal. This ILFD is implemented in SMIC 65nm CMOS technology and consumes 1.8mW from a 1.2V voltage supply excluding buffers and biasing circuits. The core area is 0.35mm× 0.73mm. The measured locking range is 13.3GHz~18.4GHz with 0dBm input power.

Published in:

Millimeter Waves (GSMM), 2012 5th Global Symposium on

Date of Conference:

27-30 May 2012

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