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Through-silicon-via built-in self-repair for aggressive 3D integration

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3 Author(s)
Nicolaidis, M. ; TIMA Lab., UJF, Grenoble, France ; Pasca, V. ; Anghel, L.

Three-dimensional (3D) integration by die-/wafer-level stacking becomes a reality, as Through-Silicon-Via technologies emerge. However, poor reliability and yield of TSV interconnects remain major challenges of this promising technology. In this paper, we propose an efficient Built-In Self-Repair (TSV-BISR) strategy for TSV faults due to manufacturing and aging defects. After interconnect tests, we replace faulty TSVs with fault-free spares using shift operations. Among the benefits of this solution is that the self-repair signals are determined on-chip without any external intervention. Moreover, we show that with TSV-BISR better reparability is achieved with fewer spares than in existing TSV repair techniques. We also show that for 3D chips with interconnect reparability targets above 98% we reduce the area needed for spares and repair logic by up to 40%.

Published in:

On-Line Testing Symposium (IOLTS), 2012 IEEE 18th International

Date of Conference:

27-29 June 2012

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