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An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

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7 Author(s)
Hegong Wei ; State Key Lab. of Analog & Mixed Signal VLSI, Univ. of Macau, Macao, China ; Chi-Hang Chan ; U-Fat Chio ; Sai-Weng Sin
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An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. With the implementation of a low-power and small-area resistive DAC and associated highly integrated circuit implementation, the proposed SAR ADC achieves rapid conversion rate, low power, and compact area, leading to SNDR of 44.5 dB and SFDR of 54.0 dB, at 400 MS/s with 1.9-MHz input. The measured FOM is 73 fJ/conversion-step at 400 MS/s from 1.2-V supply and 42 fJ/conversion-step at 250 MS/s from a 1-V supply. The active area with the digital calibration is 0.028 mm2.

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Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 11 )