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Recent advance in per-cell bit density and semiconductor technology for NAND flash memories have led to significant cost reduction in non-volatile storage implementation. However, the reliability of data stored in flash memory has dramatically decreased, requiring an efficient mechanism to detect and correct bit errors during read and write operations of the data. For this purpose, when user data are often written into a flash page, an Error Correction Code (ECC) for the data is generated and stored in the spare area of the page. ECCs tend to become longer to correct more bit errors, sometimes beyond what is affordable by the spare area. In order to cope with this problem, there have been many attempts to keep ECCs in the data area, as opposed to the spare area of the flash memory. However, an additional mapping mechanism is required to locate ECCs for a given data page, and the program time and cycle are increased due to reading/storing the ECCs. In this paper, we present a novel ECC management mechanism with an assist from PCM for NAND flash storage systems. This technique uses PCM as a temporal storage to store ECCs for the data in log blocks. Later, the pages in log blocks are merged into data blocks with their ECCs kept in the PCM. Our experimental results show that the overhead from ECC management has been improved by 57% and 69% over previous attempts in BAST and FAST mapping schemes, respectively.