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The object-oriented parallel logic simulation algorithm based on complier and sort are studied in this paper. The hardware description languages are multi-level, multi-field and standardization which proposed through the analysis of the simulation method in the existing digital systems. A digital system is described by VHDL language. The two scan VHDL source code, the compiler generates intermediate data structure are loosely coupled parallel system of workstation cluster (COW) system. The environment for parallel simulation algorithm with digital system establishment, classification, steps and synchronous communication realization is discussed beneficially.