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Implementation and optimization of AES hardcore with high performance based on Bram

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2 Author(s)
Tang Qiong ; Coll. of Inf. Eng., Zhejiang Univ. of Technol., Hangzhou, China ; Ye Jianwu

As a new generation of data encryption standard, Advanced Encryption Standard (AES) has high security, high performance, high efficiency, ease of use and flexibility, so it is widely used to encrypt sensitive commercial information and government confidential data. In this paper, after analyzing AES algorithm, the round node model based on Field Programmable Gate Arrays' (FPGAs) BlockRAM (BRAM) is designed and optimized with pipeline. The AES hardcore with unrolling architecture is implemented in the FPGA EP3SE50F484. And Its throughput reaches 62.08Gbps and the processing capacity of unit resources 45.149 Mbps/ALM. These performance indicators are superior to some research results published recently.

Published in:

Computer Science and Information Processing (CSIP), 2012 International Conference on

Date of Conference:

24-26 Aug. 2012