By Topic

Implementation and optimization of AES hardcore with high performance based on Bram

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Tang Qiong ; College of Information Engineering, Zhejiang University of Technology, Hang zhou, China ; Ye Jianwu

As a new generation of data encryption standard, Advanced Encryption Standard (AES) has high security, high performance, high efficiency, ease of use and flexibility, so it is widely used to encrypt sensitive commercial information and government confidential data. In this paper, after analyzing AES algorithm, the round node model based on Field Programmable Gate Arrays' (FPGAs) BlockRAM (BRAM) is designed and optimized with pipeline. The AES hardcore with unrolling architecture is implemented in the FPGA EP3SE50F484. And Its throughput reaches 62.08Gbps and the processing capacity of unit resources 45.149 Mbps/ALM. These performance indicators are superior to some research results published recently.

Published in:

Computer Science and Information Processing (CSIP), 2012 International Conference on

Date of Conference:

24-26 Aug. 2012