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As the networks have been broadly used everywhere such as national defense, military, bank and so on, security of data transported on network has become a hot issue. Public key cryptographic algorithms are widely applied in network communication. RSA has been used for a long time as a traditional public key cryptographic system, but it seems not able to meet user's higher security demands. In recent years, ECC(Elliptic Curve Cryptography) has been adopted more and more broadly because of its highest security of the same length bit. In addition, it also has the advantage of less computation overheads, less bandwidth demand and so on. The speed of encryption and decryption of ECC is greatly affected by point multiplication, which is very time-consuming. In this study, an FPGA(Field Programmable Gate Array) based processor is implemented for ECC, which parallelizes the computing of ECC at bit-level and gains a considerable speed-up. The ECC processor is fully implemented with hardware which supports key length of 113-bit, 163-bit and 193-bit. Algorithms suitable for hardware implementation are applied to make the processor more efficient. There are four kinds of unit in the processor: arithmetic logic unit, controlling unit, and input/output system. The units communicate with each other thought bus in FPGA device.