Referenced Items are not available for this document.
A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a 12-bit multi-channel Wilkinson (single-slope integrating) Analog-to-Digital converter (ADC). This PWLL was designed and fabricated in a 0.5- μm Silicon Germanium (SiGe) BiCMOS process. Simulation and silicon measurement data are shown that demonstrate a large improvement in the accuracy of the PVT-compensated ADC over the uncompensated ADC.
Published in:
Nuclear Science, IEEE Transactions on
(Volume:59
,
Issue:
5
)
Date of Publication: Oct. 2012
- Page(s):
- 2444 - 2450
- ISSN :
- 0018-9499
- INSPEC Accession Number:
- 13038309
- Digital Object Identifier :
- 10.1109/TNS.2012.2212722
- Product Type:
- Journals & Magazines
- Date of Publication :
- 19 September 2012
- Date of Current Version :
- 09 October 2012
- Issue Date :
- Oct. 2012
- Sponsored by :
- IEEE Nuclear and Plasma Sciences Society
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